library verilog;
use verilog.vl_types.all;
entity mltring is
    generic(
        one             : integer := 1
    );
    port(
        clk             : in     vl_logic;
        reset_b         : in     vl_logic;
        RxD             : in     vl_logic;
        TxD             : out    vl_logic;
        rceb            : out    vl_logic;
        lceb            : out    vl_logic;
        dipsw           : in     vl_logic_vector(1 downto 0)
    );
end mltring;
